Integrated circuits transistors produced using a standard complementary metal-oxide-semiconductor (CMOS) integrated circuit fabrication process, such as MOS field-effect transistors (MOSFET), have source and drain regions, and a gate electrode. The MOSFETs are typically fabricated such that each have an n-type doped polysilicon gate electrode. The source and drain regions are typically implanted into a substrate of silicon. A channel region is defined between the source and drain regions and beneath the gate electrode. Because of overlap capacitance, gate overlap of the source and drain regions is not desired. This is, a capacitance is created between the gate and source/drain regions where an overlap exits. It is desired, therefore, to minimize this overlap.
Controlling the amount of overlap between the gate and source/drain is compounded by the need to anneal the implant regions of the source/drain to meet minimum depth requirements. One technique used to control the implant spacing between the source and drain uses spacers attached to side walls of the gate electrode. Additional fabrication steps are required to create these spacers.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a transistor which has a reduced overlap capacitance while reducing the required processing steps.